The housing of semiconductor devices has assumed increasing importance with recent technological developments in the field of logic design. Large chip or die sizes, higher power dissipation and an increased input/output lead count are characteristic of such devices. It is advantageous for a wide variety of applications to mount each device in an individual, that is, single chip hermetic package.
Traditionally, high powered single chip logic die have been mounted in ceramic packages with a cavity down configuration. With this approach, the die is mounted with the back surface of the die against the top of the package, so that heat can be removed from the back or rear surface of the die. The output pins are mounted on the opposite surface. A cover or lid to provide hermetic protection for the die is also mounted on this surface. The problem with this structure is that the increasing die size requires a larger cavity and lid, forcing the input/output pins to move outboard and increasing the overall package size. This is contrary to the requirements for high performance system packaging where a smaller package with low capacity and inductance is required.
The problem of increased input/output pins and concomitant overall package size is addressed in U.S. Pat. No. 4,748,538 to Mutsuo Tsuji, entitled "Semiconductor Module". The patent illustrates a multichip configuration in which an intermediate carrier comprising a planar rectangular member with legs at its corners is disposed on a multi-layer wiring substrate. The legs provide an air space between the adjacent faces of the member and the substrate. The semiconductor chip is fixed to the face of the member within the air space. Lead wires extend outwardly from the chip and are bent to contact lead terminals on the adjacent face of the substrate. The opposite face of the substrate is populated with input/output pins coupled to the lead terminals.
What is desired, but not envisioned in the aforementioned patent, is a semiconductor package which retains the advantages of the intermediate carrier but also houses a single chip and is hermetically sealed. The present invention fills such a need.